The present invention relates generally to the semiconductor storage devices, and more particularly to latch-type sense amplifier circuits that may be used in semiconductor storage devices.
Many conventional semiconductor storage devices typically contain a number of memory cells that can generate some sort of data signal when accessed. For example, a memory cell may generate a particular current and/or voltage differential. Due the desirability of high density semiconductor storage devices, memory cells are typically manufactured to be as small as possible. Consequently, the data signal generated by a memory cell can be correspondingly small. Therefore, an important aspect of many semiconductor storage devices can be the speed at which such small memory cell signals can be amplified and thus xe2x80x9csensed.xe2x80x9d Typically, an amplifier used to detect a memory cell signal is referred to as a sense amplifier (or sense amp).
While various types of semiconductor storage devices include memory cells and sense amplifiers, one particular semiconductor storage device is currently being used in an increasing number of applications. Nonvolatile storage devices, which can include electrically erasable programmable read only memories (EEPROMs), are becoming increasingly popular due to their ability to retain data in the absence of power. Such a capability can be a valuable feature in portable electronic devices that may run off batteries.
To assist in understanding the various capabilities, features and advantages of the present invention, a conventional EEPROM and its sensing operation will now be described.
Referring now to FIG. 9, a conventional EEPROM is shown in a block schematic diagram. A conventional EEPROM may include a memory cell array 020 having a number of memory cells arranged into rows and columns. Memory cells are indicated by the character (MCkm), where k may vary from 0-i, and indicate a column, while m may vary from 0-n, and indicate a row.
In the example of FIG. 9, each memory cell may include a transistor with a floating gate. The threshold voltage of such transistors may be affected by the presence or absence of charge on their respective floating gates. In particular, a memory cell transistor may have essentially no charge on its floating gate (be in an initial condition) and therefore have an initial state threshold voltage. In addition, a memory cell transistor may have some charge, due to the addition of electrons to the floating gate (be in a programmed condition). Thus, the threshold voltage in an initial condition can be different from that of a programmed condition.
In one arrangement, memory cell transistors in an initial condition can store a value xe2x80x9c1xe2x80x9d while memory cell transistors in a programmed condition can store a value xe2x80x9c0.xe2x80x9d In a read operation, a voltage can be. applied to a control gate of a memory cell. According to the condition of the memory cell (e.g., initial or programmed condition) a particular current will flow through the memory cell. As but one example, a memory cell may include an n-channel field effect transistor with a floating gate, in which case a programmed condition will have a higher threshold voltage than an initial condition. Accordingly, in response to a voltage at its gate, a memory cell in an initial state may draw less current than a memory cell in a programmed state. In some conventions a memory cell in an initial state can be referred to as an xe2x80x9conxe2x80x9d memory cell while a memory cell in a programmed state can be referred to as a xe2x80x9coffxe2x80x9d memory cell.
In many configurations, a number of memory cells can be connected to a digit line. In a read operation, a selected memory cell can be connected to a single digit line. Thus, a typical EEPROM arrangement will detect a current drawn on a digit line when reading data from a selected memory cell. Because EEPROM memory cells usually draw a current, an EEPROM device will often include current-to-voltage (I-V) converter circuits that can converts a memory cell current into a voltage. Such a voltage may then be compared to a reference voltage and amplified in a sense amplifier to generate a logic xe2x80x9c1xe2x80x9d or xe2x80x9c0.xe2x80x9d The operation of I-V converter circuits and associated sense amplifiers will be discussed in more detail below.
In the particular EEPROM configuration of FIG. 9, memory cells (MC00-MCin) of the same row may be commonly connected to a word line. Such word lines may be connected to a word line driving circuit 010. A row decoder circuit (not shown) can decode a row address from an input signal, and provide such decoded values as inputs to a word line driving circuit 010. In response to such inputs, a word line driving circuit 010 can drive the word lines. A driven word line can connect memory cells (MC00-MCin) to digit lines, thereby selecting the memory cells (MC00-MCin).
In FIG. 9, memory cell transistors may have drains connected to digit lines DIG0-DIGi in a column-wise fashion. Digit lines (DIG0-DIGi) can be selected by a column decoder (not shown) and connected to corresponding I-V converter circuits 0300-030i in various ways. A column decoder may decode a column address to generate column select signals for selecting particular digit lines. As but one example, a column decoder may provide direct connections between digit lines (DIG0-DIGi) and I-V converter circuits (0300-030i). As but another of the many possible examples, digit lines may have a layered and/or hierarchical arrangement that includes main digit lines and sub-digit lines. In such an arrangement, the drains of memory cell transistors may be connected to sub-digit lines. A column switch circuit (not shown) may then connect a memory cell to a I-V converter circuit (0300-030i) by way of a sub-digit line and corresponding main digit line.
Referring again to FIG. 9, I-V converter circuits (0300-030i) can convert a current value, taken from the current flowing in a digit line (DIG0-DIGi) into a voltage value (SAVD0-SAVDi). Such a voltage value can then be supplied to sense amplifier circuits (0500-050i).
An EEPROM according to FIG. 9 may fewer include a reference cell 021 and corresponding I-V converter circuit, also referred to as a reference voltage generating circuit 040. In one particular arrangement, a reference cell 021 may include an on (initial condition) cell, shown as xe2x80x9cON Cellxe2x80x9d and an off (programmed condition) cell, shown as xe2x80x9cOFF Cell.xe2x80x9d An on cell current can be drawn in a digit line DIGRON connected to the ON Cell. An off cell current can be drawn on a digit line DIGROFF connected to the OFF Cell.
A reference voltage generating circuit 040 can receive current values from the DIGRON and DIGROFF lines as inputs. In response to such inputs, a reference voltage generating circuit 040 may generate a reference voltage VREF that can be halfway between a voltage generated in response to the DIGRON current and a voltage generated in response to a DIGROFF current.
As shown in FIG. 9, each sense amplifier circuit (0500-050i) may include a first input SA1 and second input SA2. A first input SA1 may receive an input voltage SAVD0-SAVDi from a corresponding I-V converter circuit (0300-030i). The second inputs SA2 can receive a reference voltage VREF from reference voltage generating circuit 040.
Sense amplifier circuits (0500-050i) may further receive a sense amplifier latch activating signal BSAL. In response to the sense amplifier latch activating signal BSAL, each sense amplifier circuit (0500-050i) can latch and amplify a voltage difference between its inputs SA1 and SA2. Such amplified voltage differences may be provided as amplifier output signals TDIO0-TDIOi.
Amplifier output signals TDIO0-TDIOi may be provided to an internal bus 060. Amplifier output signals (TDIO0-TDIOi) on an internal bus, 060 may then be provided as on output terminals as data out values DO0-DOi.
It is noted that the various sense amplifier circuits (0500-050i) of FIG. 9 may be latch-type sense amplifiers. FIG. 10 shows one example of a latch-type sense amplifier.
Referring now to FIG. 10, a conventional latch-type sense amplifier may include input transistors NM1 and NM2. In the particular example illustrated, input transistors (NM1 and NM2) may include n-channel field effect transistors. Input transistor NM1 may have a source-drain path connected between an input terminal SA1 and an amplifier terminal A1. Similarly, input transistor NM2 may have a source-drain path connected between an input terminal SA2 and an amplifier terminal A2. The gates of input transistors NM1 and NM2 may commonly receive a sense amplifier activating signal /SE. A sense amplifier activating signal /SE can correspond to sense amplifier latch activating signal BSAL shown in FIG. 9. An input terminal SA1 may receive a voltage corresponding to a memory cell data value. Such a voltage may be provided by a I-V converter circuit, for example. An input terminal SA2 may receive a reference voltage VREF that may be provided by a reference voltage generating circuit, for example.
It is understood that input transistors NM1 and NM2 may include sources connected to input terminals (SA1 and SA2) and drains connected to amplifier terminals (A1 and A2), or vice versa. Thus, such transistors may be conceptualized as including one source/drain terminal connected to an input (SA1 or SA2) and another source/drain terminal that is connected to an amplifier terminal (A1 or A2).
In the operation of a latch-type sense amplifier of FIG. 10, a sense amplifier activating signal /SE may initially be high, turning on input transistors NM1 and NM2. Once a differential voltage is generated between input terminals SA1 and SA2 (and hence between amplifier terminals A1 and A2), a sense amplifier activating signal /SE can transition low, turning off input transistors NM1 and NM2. A latch circuit 001 may then amplify and latch the voltage differential between amplifier terminals (A1 and A2).
A more detailed example of a latch-type sense amplifier circuit will now be described with reference to FIG. 11.
A latch-type sense amplifier circuit according to FIG. 11 may include some of the same general constituents as the circuit of FIG. 10. In particular, FIG. 11 shows a sense amplifier latch activating signal BSAL which can correspond to the sense amplifier activating signal /SE of FIG. 10. Further, FIG. 11 includes input transistors NM59 and NM60, which can correspond to input transistors NM1 and NM2 of FIG. 10. In addition, FIG. 11 shows a latch circuit 001 that can correspond to the latch circuit 001 of FIG. 10. A first node N1 of latch circuit 001 can correspond to a amplifier terminal A1, a second node N2 of latch circuit 001 can correspond to a amplifier terminal A2.
A latch circuit 001 in FIG. 11 may include circuits that can amplify and latch a voltage differential generated between a first node N1 and a second node N2. As but one example, a latch circuit 001 may include cross-coupled inverters, where the input of a first inverter and output of a second inverter are connected to a first node N1, while the input of the second inverter and output of the first inverter are connected to a second node N2.
In the very particular example of FIG. 11, a latch circuit 001 may include a first complementary metal-oxide-semiconductor (CMOS) inverter that includes transistors PM51 and NM51, a second CMOS inverter that includes transistors PM52 and NM52, a first supply device that includes transistor PM53, and a second supply device that includes transistor NM53. A first supply transistor PM53 may be a p-channel transistor with a source connected to a first supply voltage VDD, a gate that receives a sense amplifier latch activating signal BSAL, and a drain that is commonly connected to the sources of first inverter transistor PM51 and second inverter transistor PM52. First and second inverter transistors (PM51 and PM52) may be p-channel transistors.
A second supply transistor NM53 may be an n-channel transistor with a source connected to a second supply voltage VSS, a gate that receives the sense amplifier latch activating signal BSAL as inverted by an inverter INV52, and a drain that is commonly connected to the sources of first inverter transistor NM51 and second inverter transistor NM52. First and second inverter transistors (NM51 and NM52) may be n-channel transistors.
The drains of first inverter transistors (PM51 and NM51) and gates of second inverter transistors (PM52 and NM52) may be commonly connected to a first node N1. Similarly, the drains of second inverter transistors (PM52 and NM52) and gates of first inverter transistors (PM51 and NM51) may be commonly connected to a second node N2.
A latch circuit included in a sense amplifier is further described Japanese Laid-Open Patent Publication No. 4-119597.
A conventional latch-type sense amplifier may further include various output circuits. In the particular arrangement of FIG. 11, such output circuits include a first node driver, formed by first node driver transistors PM54 and NM54, a second node driver, formed by second node transistors PM55 and NM55, and a driver supply device NM56. In addition, such output circuits may further include disable devices PM56 and PM57, as well as output inverters INV53, INV54 and INV55. An output signal TDIOk from a conventional latch-type sense amplifier circuit may be generated by an output stage that includes driver transistors PM58 and NM58.
In the example of FIG. 11, a first node driver may take the form of a CMOS inverter and include an input connected to node N1 and an output connected to a first output control node N3. Similarly, a second node driver may take the form of a CMOS inverter having an input connected to node N2 and an output connected to a second output control node N4. First and second node driver transistors PM54 and PM55 may be p-channel transistors having sources connected to a power supply voltage VDD. First and second node driver transistors NM54 and NM55 may be n-channel transistors having sources connected to the source-drain path of driver supply device NM56.
In the particular arrangement of FIG. 11, driver supply device NM56 may include an n-channel transistor having a drain commonly connected to the sources of first and second node driver transistors NM54 and NM55, a source connected to a second power supply voltage VSS, and a gate that receives an inverted sense amplifier latch activating signal SAL from inverter INV52.
Output control node N3 may be connected to the output of first node driver PM54/NM54 and to the input of output inverter INV53. At the same time, output control node N4 may be connected to the output of second node driver PM55/NM55 and to the input of output inverter INV55. Both output control nodes (N3 and N4) can be placed at a disable potential by disable devices PM56 and PM57. More particularly, output disable devices PM56 and PM57 may be p-channel transistors having drains connected to output control nodes N3 and N4, respectively, sources connected to a first power supply voltage VDD, and gates connected to the output of an inverter INV51. Inverter INV51 can invert a sense amplifier latch activating signal BSAL to generate the signal inverse SAL. In the particular example of FIG. 11, a disable potential may be the first power supply potential, as will be described in more detail below.
Referring again to FIG. 11, inverters INV53 and INV54 can be connected in series between a first output control node N3 and a first driver device PM58. Inverter INV55 can be connected between a second output control node N4 and a second driver device NM58. In the example of FIG. 11, first driver device PM58 can include a p-channel transistor while second driver device NM58 may include an n-channel transistor. More particularly, first driver device PM58 can have a source connected to a first power supply voltage VDD, a drain connected to an output node, and a gate connected to the output of inverter INV54. A second driver device NM58 can include an n-channel transistor having a source connected to a low power supply voltage VSS, a drain connected to the output node (and hence the drain of first driver device P58), and a gate connected to the output of inverter INV55. Driver devices PM58 and NM58 may function as an output stage buffer circuit that drives an internal bus with an amplifier output TDIOk (where k may vary from 1 to i).
It is noted that power supply voltages are not necessarily limited to external voltages supplied to a semiconductor storage device. As but one example, a first power supply voltage VDD may be a xe2x80x9cstepped-downxe2x80x9d voltage generated by reducing an externally supplied voltage.
Having described the various portions of the particular latch-type sense amplifier circuit of FIG. 11, the operation of the circuit will now be described.
A sense amplifier latch activating signal BSAL may be initially inactive (high in example). With the BSAL signal high, input transistors NM59 and NM60 may be turned on, allowing a differential voltage to be developed across nodes N1 and N2. For example, with input transistor NM59 turned on, an output voltage from an I-V converter circuit SAVDk can be placed on a node N1 while a reference voltage VREF from a reference voltage generating circuit can be placed on node N2.
Within latch 001, with BSAL inactive, first supply device PM53 can be turned off, isolating cross-coupled inverters (PM51/NM51 and PM52/NM52) from a high power supply voltage VDD. Similarly, a low SAL signal generated by inverter INV52 can turn off second supply device NM53, isolating cross-coupled inverters (PM51/NM51 and PM52/NM52) from a low power supply voltage VSS. In this way, an inactive BSAL signal can result in latch 001 being inactive.
In addition, with the BSAL signal inactive, a low SAL signal can turn off driver supply device NM56. With NM56 turned off, first and second node drivers (PM54/NM54 and PM55/NM55) can be isolated from a low power supply voltage, and thus deactivated. Further, an inactive BSAL signal can result in disable devices PM56 and NM56 being turned on. Thus, a first output control node N3 and second output control node N4 can be placed at a high potential.
A high potential at first output control node N3 can result in the gate of first driver device PM58 being driven high by inverters INV53 and INV54. Consequently, first driver device PM58 can be turned off. A high value at second output control node N4 can result in the gate of second driver device NM58 being driven low by inverter INV55. Consequently, second driver device NM58 can be turned off. In this way, an inactive BSAL signal can result in an output driver stage PM58/NM58 being inactive and an output terminal being placed in a high-impedance state.
A sense amplifier latch activating signal BSAL may then transition to an active state (low in this example). With the BSAL signal low, input transistors NM59 and NM60 may be turned off, isolating a differential voltage on nodes N1 and N2 from input nodes SA1 and SA2. As noted above, such a differential voltage may be the difference between the output of an I-V converter circuit SAVDk and a reference voltage VREF.
Within latch 001, with BSAL active, first supply device PM53 can be turned on, supplying cross-coupled inverters (PM51/NM51 and PM52/NM52) with a high power supply voltage VDD. In addition, a high SAL signal generated by inverter INV52 can turn on second supply device NM53, supplying a low power supply voltage VSS to cross-coupled inverters (PM51/NM51 and PM52/NM52). In this way, an active BSAL signal can result in the activation of latch 001.
With latch 001 active, nodes N1 and N2 can be driven to complementary values according to the initial potential across the nodes (N1 and N2) thereby latching a data value. For example, if a potential at node N1 (SAVDk) was greater than that at node N2 (VREF), node N1 could be driven to a high power supply voltage VDD while node N2 could be driven to a low power supply voltage VSS. Such an operation may be the case when a memory cell in an initial condition is read. Conversely, a potential at node N1 (SAVDk) can be less than that at node N2 (VREF). As a result, node N1 could be driven to the low power supply voltage VSS while node N2 could be driven to the high power supply voltage VDD. Such an operation can occur when a memory cell in a programmed condition is read. In this way, an active BSAL signal can result in an input signal being amplified and latched in latch 001.
In addition, with the BSAL signal active, a high SAL signal can turn on driver supply device NM56, thereby enabling first and second node drivers (PM54/NM54 and PM55/NM55). At essentially the same general time, disable devices PM56 and PM57 can both be turned off. Once enabled, first and second node drivers (PM54/NM54 and PM55/NM55) can drive output control nodes N3 and N4 according to the potential at nodes N1 and N2, respectively. More particularly, if nodes N1 and N2 are driven high and low, respectively, nodes N3 and N4 can be driven low and high respectively. Further, if nodes N1 and N2 are driven low and high, respectively, nodes N3 and N4 can be driven high and low, respectively. In this way, when the BSAL signal is active, nodes N3 and N4 can be driven to complementary values according to a data value in latch 001.
First and second driver devices (PM58 and NM58) can be controlled according to the various potentials at output control nodes N3 and N4. Thus, when output control nodes N3 and N4 are high and low, respectively, inverters INV53 and INV54 can drive the gate of first driver device PM58 high, thereby turning off first driver device PM58. At the same time, inverter INV55 can drive the gate of second driver device NM58 high, thereby turning on first driver device NM58, and driving amplifier output TDIOk low. In this way, a low output value can be generated when a latch 001 is activated and a node N1 is at a lower potential than a node N2. When output control nodes N3 and N4 are low and high, respectively, inverters INV53 and INV54 can drive the gate of first driver device PM58 low, thereby turning on first driver device PM58 and driving internal bus TDIOk high. At the same time, inverter INV55 can drive the gate of second driver device NM58 low, thereby turning off first driver device NM58. In this way, a high output value can be generated when a latch 001 is activated and a node N1 is at a higher potential than a node N2.
Referring now to FIG. 12, the operation of a non-volatile semiconductor storage device will now be described that includes a conventional latch-type sense amplifier, such as that shown in FIGS. 10 and 11. FIG. 12 is a timing diagram that shows applied address values A1, a sense amplifier activating signal BSA, a precharging signal TSAPC, a sense amplifier latch activating signal BSAL, an internal bus output signal (amplifier output signal) TDIOk, and a data output signal DOk.
Referring now to FIG. 12 in conjunction with FIG. 9, at time t1, an address can make a transition to a new read address. Such a read address may be decoded by a row address decoder and a column address decoder (both not shown).
At time t2, a sense amplifier activation signal BSA can become active (low in this example). An active sense amplifier activation signal BSA can activate I-V converter circuits 030k (where k=0-i) and a reference voltage generating circuit 040. Also at time t2, an equalization signal TSAPC can be activated. An active equalization signal TSAPC can precharge digit lines DIG0-DIGi to a predetermined potential.
At time t3, an equalization signal TSAPC can return to an inactive state, disabling precharge circuits. Thereafter, in response to the applied read address A1, at least one memory cell can be selected, resulting in current being drawn on a digit line. Such a current can be converted to a voltage by a I-V converter circuit 030k and the resulting voltage SAVDk can be applied to a first input of a latch-type sense amplifier 050k. Because a sense amplifier latch activating BSA can be inactive, such a voltage can be provided to a latch circuit node within the sense amplifier. At the same general time, a reference voltage generating circuit 040 can generate a reference voltage VREF in response to DIGRON and DIGROFF currents. Such a reference voltage VREF can be applied to a second input of a latch-type sense amplifier 050k. Because a sense amplifier latch activating BSA can be inactive, such a voltage can be provided to another latch circuit node within the sense amplifier.
Between times t4 and t5, a sense amplifier latch activating signal BSAL can be activated, resulting in latch-type sense amplifiers 050k amplifying and latching a data value. Thus, an internal bus output signal TDIOk can transition (assuming a change in data value) between times t4 and t5. A corresponding transition can then occur for a data output signal DOk.
While a conventional approach such as that shown in FIGS. 9-12 may provide sensing of memory cell data values, such a conventional approach may include drawbacks.
One drawback can include noise generated at sense amplifier inputs due to capacitive coupling of a sense amplifier enable signal /SE (and BSAL). More particularly, if reference is made to both FIGS. 10 and 11, a parasitic capacitance C0 may exist between the gates and drains of input transistors (NM1 and NM2, NM59 and NM60). These input transistor gates may receive a sense amplifier enable signal /SE (or BSAL). However, in operation, a parasitic load capacitance may also be connected input nodes SA1 and SA2. For example, an additional parasitic capacitance C1 can be connected to input node SA1 while an additional parasitic capacitance C2 can be connected to input node SA2. Further, there can be a considerable difference in capacitance between C1 and C2. Thus, variations in potential due to noise can differ between first and second inputs SA1 and SA2. Such variations due to noise will now be described in more detail.
In a conventional sense amplifier, such as that shown in FIG. 10, when a sense amplifier enable signal /SE transitions from a high level to a low level, noise can be generated at first input SA1 due to the gate-drain capacitance Cgd of input transistor NM1. Simultaneously, noise can be generated at second input SA1 due to gate-drain capacitance of input transistor NM2. In FIG. 10, the gate-drain capacitance of transistors NM1 and NM2 are shown as C0. Of course, if the transistor terminals connected to input nodes SA1 and SA2 were sources, a parasitic capacitance C0 could be considered a gate-source capacitance Cgs of transistors NM1 and NM2.
As previously shown in FIG. 9, a first input SA1 of the various sense amplifiers (0500-050i) may include a first input SA1 that is connected to a particular I-V converter circuit (0300-030i). The capacitance of such a connection can be represented by a load capacitance C1 and is shown by example in FIG. 9 at the output of I-V converter circuit 0300. In addition, each sense amplifier (0500-050i) may also include a second input SA2 connected to a reference voltage generating circuit 040. The capacitance of such a connection can be represented by a load capacitance C2 and is shown by example in FIG. 9 at the output of reference signal generating circuit 040.
Because a reference voltage generating circuit 040 may be connected to many sense amplifiers (0500-050i), and a I-V converter circuit (0300-030i) may be connected to one sense amplifier (0500-050i), a load capacitance C2 may be considerably larger than a load capacitance C1. As but one example, in an arrangement such as that shown in FIG. 9, the number of sense amplifiers could be eight. In such a case, a load capacitance C2 at the output of a reference voltage generating circuit 040 can be approximately eight times that of a load capacitance C1 at the output of a I-V converter circuit (0300-030i).
A resulting voltage change at the inputs of a sense amplifier circuit due to noise will now be described in more detail. It will be assumed that a sense-amplifier circuit can include input transistors such as NM1 and NM2 (FIG. 10) or NM59 and NM60 (FIG. 11) connected to inputs SA1 and SA2. Such transistors may include a gate-drain capacitance Cgd (if transistors drains are connected to inputs SA1 and SA2) or a gate-source capacitance Cgs (if transistors sources are connected to inputs SA1 and SA2) of C0. Further, as described above, circuitry, including an interconnect or the like, can present a load capacitance at input SA1 of C1 and a load capacitance at input SA1 of C2. It will further be assumed that the gates of such input transistors can receive a signal (such as /SE in FIG. 10 or BSAL in FIG. 11) that makes a transition having an amplitude of V.
A potential change VSA1 at input node SA1 due to capacitive coupling can approximately be given as set forth below.
VSA1=(C0/(C0+C1))xc3x97V
A potential change VSA2 at input node SA2 due to capacitive coupling can approximately be given as set forth below.
VSA2=(C0/(C0+C2))xc3x97V
As noted above, C2 may be considerably larger than C1. Consequently, a change in potential VSA1 can be larger than the change in potential VSA2.
A difference in the change of potential at input nodes SA1 and SA2 may lead to slower or even erroneous read operations. This may be understood with reference to FIG. 13.
FIG. 13 is a timing diagram generated by a circuit simulation SPICE(copyright) that shows the response of a conventional latch-type sense amplifier such as that shown in FIG. 12. FIG. 13 includes various responses and signal. A sense amplifier latch activating signal BSAL can transition from a high level to a low level. Also included are two output signals TDIOi(ON) and TDIOi(OFF). TDIOi(ON) can represent an output signal corresponding to an xe2x80x9conxe2x80x9d memory cell (i.e., a memory cell in an initial condition). TDIOi(OFF) can represent an output signal corresponding to an xe2x80x9coffxe2x80x9d memory cell (i.e., a memory cell in a programmed condition).
Input waveforms corresponding to such different types of memory cells are also shown. A waveform SAVDi(ON) can represent the voltage at a first input, such as SA1, that may result when an on memory cell is read. A waveform SAVDi(OFF) can represent the voltage at a first input, such as SA1, that may result when an off memory cell is read. Responses SAVDi(ON) and SAVDi(OFF) may be provided by a I-V converter circuit, or the like. A waveform VREF can represent the voltage at a second input, such as SA2. Such a voltage may be provided by a reference voltage generating circuit, or the like. Thus, if an on memory cell is read, the voltage at node SA1 (SAVDi(ON)) can initially be greater than VREF. Conversely, if an off memory cell is read, the voltage at node SA1 (SAVDi(OFF)) can initially be less than VREF.
Various responses to inputs to a latch circuit within a sense amplifier are also shown. In particular, the response at a first latch input for an on memory cell is shown as A1(ON), while the response at a first latch input for an off memory cell is shown as A1(OFF). Similarly, response at a second latch input for an on memory cell is shown as A2(ON), while the response at a second latch input for an off memory cell is shown as A2(OFF).
Thus, ideally, when an on (e.g., initial condition) memory cell is read, SA1 can remain above VREF. This difference in potential can be amplified and latched by a latch to cause A1(ON) to go high and A2(ON) to go low. When an off (e.g., programmed) memory cell is read, ideally, SA1 can remain below VREF. This difference in potential can be amplified and latched by a latch to cause A1(OFF) to go high and A2(OFF) to go low.
However, noise due to capacitive coupling can produce non-ideal responses. For example, as shown in FIG. 13, a sense amplifier latch activating signal BSAL can transition from high to low. Due to capacitive coupling, such a transition can result in a voltage drop at a first input SA1. This is represented in FIG. 13 by a dip in the values of SAVDi(ON) and SAVDi(OFF) at time TA. Further, due to the differences in load capacitance between a first input SA1 and a second input SA2, a voltage drop at a second input SA2 can be considerably smaller. Thus, as shown in FIG. 13, at time TA, a response SAVDi(ON) at a first input SA1 may undesirably fall below a reference voltage VREF at a second input SA2.
In one particular example, prior to a transition in the sense amplifier latch activating signal BSAL, the difference between the voltage at a first node SA1 (SAVDi(ON) and/or SAVDi(OFF)) and the voltage at a second node SA2 (VREF) can be as small as 50 mV. However, a voltage change due to a transition in a BSAL signal and capacitive coupling can result in changes at a first node SA1 (SAVDi(ON) and/or SAVDi(OFF)) that can be high as high as 100 mV. At the same time, due to differences in load capacitance, a corresponding voltage change at a second node SA2 (VREF) that can be as small as several tens of mV.
If sensing (i.e., amplification and/or latching of a value at first and second inputs SA1 and SA2) occurs while noise due to switching is present at the inputs, erroneous results may occur as a value SAVDi(ON) may be less than that of VREF. Thus, to avoid such erroneous results, conventional approaches may have to wait until a proper differential is developed by a sense amplifier (i.e., the inputs are essentially free of such noise from switching). Said in another way, sufficient timing margin can be included in a sense amplifier activation operation to ensure input nodes are at a desired level before a sense amplifier amplifies data.
In light of the above discussion, it would be desirable to arrive at some way of improving the sensing speeds of a semiconductor storage device. More particularly, it would be desirable to improve the sensing speed of a semiconductor storage device that may include I-V converter circuits that convert a memory cell current to a voltage that can be sensed by a latch-type sense amplifier.
According to the disclosed embodiments of the present invention, a semiconductor storage device may include current-to-voltage (I-V) converter circuits can be connected to digit lines. A current may flow through a digit line when a memory cell is selected. A current on a digit line may be converted into a voltage by an I-V converter circuit, and the voltage may be provided as one input to a latch-type sense amplifier. A reference voltage generator circuit may provide a reference voltage to other inputs of a number of latch-type sense amplifiers.
Within each latch-type sense amplifier, a first input may be connected to a first amplifier node by a first transfer switch. A second input may be connected to a second amplifier node by second transfer switch. A first transfer switch may include a first transistor that receives a control signal at a first control gate and a second. transistor that receives a complementary control signal at a second control gate. A second transistor may include a parasitic capacitance equivalent to that of the first transistor. A transition in the control signal can generate a first noise component at the first input due to the parasitic capacitance of the first transistor. However, a corresponding opposite transition in the complementary control signal can generate a second noise component at the first input that can cancel at least a portion of the first noise component.
According to one aspect of the embodiments, a first transistor may include an n-channel transistor and a second transistor may include a p-channel transistor. The source-drain paths of first and second transistors may be connected in parallel between the first input and the first amplifier node.
According to another aspect of the embodiments, the first and second transistors may both include n-channel transistors. The source-drain paths of the first transistor may be connected between the first input and the first amplifier node. The source and drain of the second transistor may be commonly connected to the first input.
According to another aspect of the embodiments, the third transistor may include an n-channel transistor having a source-drain path connected between the second input and the second amplifier node.
According to another aspect of the embodiments, a second transfer switch may include a fourth transistor. A fourth transistor can be a p-channel transistor and have the complementary control signal at its gate and include a source-drain path connected between the second input and the second amplifier node. Alternatively, a fourth transistor may include an n-channel transistor with a source and drain commonly connected to the second input.